It is well known that superior performance can be obtained from devices integrated on semiconductor chips, when such devices, or groups of devices, are electrically isolated from each other on the chip substrate. In this manner, all undesirable parasitic coupling between such devices is eliminated, and all desired electrical connections are accomplished by interconnect paths formed on the surface of the substrate.
When integrated circuit devices, or circuits, are entirely isolated from the substrate, the prevalent latch-up in CMOS circuits is eliminated, and parasitic capacitances of all types of circuits are substantially reduced. With reduced parasitic capacitances, the circuits can operate at faster speeds.
Recent developments in semiconductor processing techniques have led to the silicon on isolator (SOI) technology which allows circuits to be entirely electrically isolated from the semiconductor substrate. The SOI technology involves the formation of a silicon dioxide (oxide) between the semiconductor substrate and an overlying semiconductor layer for forming therein the devices or circuits. The device semiconductor layer is thus electrically isolated from the substated. Moreover, the device semiconductor layer itself is further processed to isolate sections thereof corresponding to specific device or circuit areas. The device semiconductor layer is typically sectioned by trench structures, and thereafter the trenches are filled with an isolation dielectric, thereby forming semiconductor islands entirely isolated from each other and the chip substrate.
One technique for forming the isolation layer between the substrate and the device semiconductor layer involves the anodization of a heavily doped semiconductor sublayer and its subsequent oxidation to form a silicon oxide dielectric. Such a technique is disclosed in pending U.S. patent application entitled "High Definition Anodized Sublayer Boundary", identified above. Another SOI isolation technique is disclosed in U.S. Pat. No. 4,628,591, by Zorinsky et al., the subject matter of which is incorporated herein by reference. As is well known in the art, the use of a semiconductor material heavily doped with an electrically active impurity is advantageous for anodization purposes. Such a sublayer heavily doped with, for example, a phosphorus impurity, provides a preferential anodizable sublayer, in that such highly doped layer becomes anodized much before other more lightly doped adjacent semiconductor layers. While such a highly doped sublayer is well adapted for preferentially anodizing a selected area, the dopants tend to diffuse into the overlying device semiconductor layer, thereby degrading the performance of the devices formed therein. In order to fabricate high performance devices, subsequent process steps must be undertaken to remove the undesired up-diffusions, such as counterdoping techniques.
From the foregoing, it can be seen that a need exists for an improved technique for forming an isolated sublayer which eliminates the up-diffusion of impurities so that adjacent semiconductor areas remain unaffected by the formation of the isolation sublayer. Another need exists for an improved SOI technique which can be easily employed using currently available semiconductor processing apparatus and methods.